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Stress-Aware Module Placement on Reconfigurable Devices
- J. Angermeier, Daniel Ziener, M. Glaß, J. Teich
- Computer Science21st International Conference on Field…
- 5 September 2011
A new aging model is applied to estimate the influence of aging effects on dynamically reconfigurable devices, and which can be evaluated at runtime, while providing quite accurate aging results.
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library
- C. Dennl, Daniel Ziener, J. Teich
- Computer ScienceIEEE 20th International Symposium on Field…
- 29 April 2012
This paper introduces a novel FPGA-based methodology for accelerating SQL queries using dynamic partial reconfiguration and shows that it is able to achieve a substantially higher throughput compared to a software-only solution.
Netlist-level IP protection by watermarking for LUT-based FPGAs
- M. Schmid, Daniel Ziener, J. Teich
- Computer ScienceInternational Conference on Field-Programmable…
- 1 December 2008
This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature…
FPGA-Based Dynamically Reconfigurable SQL Query Processing
- Daniel Ziener, Florian J. Bauer, Helmut Weber
- Computer ScienceACM Trans. Reconfigurable Technol. Syst.
- 22 August 2016
An FPGA-based SQL query processing approach exploiting the capabilities of partial dynamic reconfiguration of modern FPGAs and a performance analysis is introduced that is able to estimate the processing time of a query for different processing strategies and different communication and processing architecture configurations.
Partial reconfiguration on FPGAs in practice — Tools and applications
A survey on state-of-the-art trends on reconfigurable architectures and devices, application specific requirements, and design techniques and tools that are essential for implementing partial run-time reconfiguration on FPGAs, and a demonstration of the floorplanning and constraint generation tool GoAhead.
FPGA core watermarking based on power signature analysis
This is the first watermarking method, where the signature is extracted in this way, and the authors were able to sign cores at the netlist as well as the bitfile level, so a wide spectrum of cores can be protected.
Power Signature Watermarking of IP Cores for FPGAs
This is the first watermarking method where the signature (watermark) is detected at the power supply pins of the FPGA, and a detection algorithm is introduced which can decode the signature from a voltage trace with high reliability.
Throughput Optimizations for FPGA-based Deep Neural Network Inference
Using the Power Side Channel of FPGAs for Communication
- Daniel Ziener, Florian Baueregger, J. Teich
- Computer Science18th IEEE Annual International Symposium on Field…
- 2 May 2010
A novel technique for transmitting data over the power supply pins of an FPGA, which achieves data rates up to 500 kbit/s and an encoding/decoding method which is independent of the board type andFPGA combination is presented.
Energy-aware SQL query acceleration through FPGA-based dynamic partial reconfiguration
- Andreas Becher, Florian J. Bauer, Daniel Ziener, J. Teich
- Computer Science24th International Conference on Field…
- 20 October 2014
The implementation of this flexible FPGA-based query accelerator approach on the embedded low-energy system-on-chip (SoC) platform Xilinx Zynq shows SQL query processing speeds comparable to high-end database servers, however, at a much lower energy consumption.