Daniel Ziener

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Jürgen Teich50
Dirk Koch16
William H. Mangione-Smith13
John Lach13
Miodrag Potkonjak13
55Jürgen Teich
12Stefan Wildermann
10Andreas Becher
10Dirk Koch
6Jedrzej Kufel

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2016
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A Self-Adaptive SEU Mitigation System for FPGAs with an Internal Block RAM Radiation Particle Sensor
In this paper, we propose a self-adaptive FPGA-based, partially reconfigurable system for space missions in order to mitigate Single Event Upsets in the FPGA configuration and fabric. Dynamic reconfiguration is used here for an on-demand replication of modules in dependence of current and changing radiation levels. More precisely, the idea is to trigger a… (More)
Netlist-level IP protection by watermarking for LUT-based FPGAs
This paper presents a novel approach to watermark FPGA designs on the netlist level. We restrict the dynamically addressable part of the logic table, thus freeing space for insertion of signature bits into lookup tables (LUTs). In this way, we tightly integrate the watermark with the design so that simply removing mark carrying components would damage the… (More)
Acceleration of SQL Restrictions and Aggregations through FPGA-Based Dynamic Partial Reconfiguration
SQL query processing on large database systems is recognized as one of the most important emerging disciplines of computing nowadays. However, current approaches do not provide a substantial coverage of typical query operators in hardware. In this paper, we provide an important step to higher operator coverage by proposing a) full dynamic data path… (More)
Power Signature Watermarking of IP Cores for FPGAs
— In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This is the first watermarking method where the signature is extracted in this way. We are able to sign IP cores at the netlist as well as the bitfile level, so a wide spectrum of… (More)
On-the-fly Composition of FPGA-Based SQL Query Accelerators Using a Partially Reconfigurable Module Library
In this paper, we introduce a novel FPGA-based methodology for accelerating SQL queries using dynamic partial reconfiguration. Query acceleration is of utmost importance in large database systems to achieve a very high throughput. Although common FPGA-based accelerators are suitable to achieve such a high throughput, their design is hard to extend for new… (More)
Identifying FPGA IP-Cores Based on Lookup Table Content Analysis
In this paper we introduce a new method to identify IP cores in an FPGA by analyzing the content of lookup tables. This technique can be used to identify registered cores for IP protection against unlicensed usage. We show methods to extract the content of the lookup tables in a design from a binary bitfile of Xilinx Virtex-II and Virtex-II Pro FPGAs. To… (More)
Stress-Aware Module Placement on Reconfigurable Devices
A lot of research has been spent on improving the reliability and extending the lifetime of ASIC and SoC devices, but only little on improving the long-term reliability of dynamically reconfigurable systems. In order to increase the lifetime of a reconfigurable device, we propose a placement strategy to distribute the stress equally on the reconfigurable… (More)