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As digital microfluidics-based biochips find more applications, their complexity is expected to increase significantly owing to the trend of multiple and concurrent assays on the chip. There is a pressing need to deliver a top-down design methodology that the biochip designer can leverage the same level of computer-aided design support as the semi-conductor(More)
The paper presents an area- and power-efficient implementation of an image compressor for wireless capsule endoscopy application. The architecture uses a direct mapping to compute the two-dimensional discrete cosine transform which eliminates the need of transpose operation and results in reduced area and low processing time. The algorithm has been modified(More)
Physical activity monitoring of the elderly people provides valuable information for health aware services. This paper presents the implementation of a system to sense, send, display and store physiology activity. The system includes a wearable device to be worn by the individual to collect physical activity data, a wireless communication link between the(More)
The FANFARE (Falls And Near Falls Assessment Research and Evaluation) project has developed a system to fulfill the need for a wearable device to collect data for fall and near-falls analysis. The system consists of a computer and a wireless sensor network to measure, display, and store fall related parameters such as postural activities and heart rate(More)
The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been(More)
The paper presents a new and fast algorithm to efficiently compute radix-10 logarithm of a decimal number. The algorithm uses 32-bit floating-point arithmetic, and is based on a digit-by-digit iterative computation that does not require look-up tables, curve fitting, decimal-binary conversion, or division operations; the number of iterations depends on the(More)
This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal logarithmic converter. Two approaches, binary-based decimal approximation algorithm (Algorithm 1) and decimal linear approximation algorithm (Algorithm 2), are proposed and investigated. It shows that decimal linear approximation algorithm (Algorithm 2) is(More)
This paper presents a new design and implementation of a 32-bit decimal floating-point (DFP) antilogarithmic converter based on the digit-recurrence algorithm with selection by rounding. The converter can calculate the accurate antilogarithm (10) of the 32-bit DFP numbers which are defined in the IEEE 754-2008 standard. The sequential architecture of the(More)