Daniel M. Dreps

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A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used in a source-synchronous link configuration. The design of the receiver was optimized for power owing to the assumption that a link protocol enables a periodic calibration during which the circuit does not have to deliver valid data. In addition, it is shown that the(More)
Quadrature-phase clock generation is required for many applications in wireless and wireline communications. Traditional closedloop-based quadrature-generation methods using DLLs or PLLs require high power, large area and long lock-in time. Open-loop quadrature generators address many of the issues associated with closed-loop designs. The polyphase filter(More)
POWER8TM delivers a data-optimized design suited for analytics, cognitive workloads, and today’s exploding data sizes. The design point results in a 2.5x performance gain over its predecessor, POWER7+TM, for many workloads. In addition, POWER8 delivers the efficiency demanded by cloud computing models and also represents a first step toward creating an open(More)
We explore two schemes using transmissionline (T-line) to achieve high-performance global interconnects on VLSI chips. For both schemes, we select wire dimensions to ensure T-line effects present and employ inverter chains as drivers and receivers. In order to achieve high throughput and alleviate Inter-Symbol Interference (ISI), high termination resistance(More)