Daniel L. Rosenband

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It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog incurs a performance penalty. The case study here shows that this need not be the case. If the higher-level language has suitable semantics, it is possible to synthesize hardware that is competitive with hand-written Verilog RTL. Differences in the hardware quality(More)
A modular synthesis flow is essential for a scalable and hierarchical design methodology. This paper considers a particular modular flow where each module has interface methods and the internal behavior of the module is described in terms of a set of guarded atomic actions on the state elements of the module. A module can also read and update the state of(More)
We present a new hardware synthesis methodology for guarded atomic actions (or rules), which satisfies performance-related scheduling specifications provided by the designer. The methodology is based on rule composition, and relies on the fact that a rule derived by the composition of two rules behaves as if the two rules were scheduled simultaneously. Rule(More)
The quality of high-level synthesis results is strongly dependant on the concurrency that can be found in designs. In this paper we introduce the Ephemeral History Register (EHR), a new primitive state element that enables concurrent scheduling of arbitrary rules in a rule-based design framework. The key properties of the EHR are that it allows multiple(More)
This paper describes StarT-Voyager, a machine designed as an experimental platform for research in cluster system communication. The heart of StarT-Voyager is a network interface unit (NIU) that connects the memory bus of a PowerPC-based SMP to the MIT Arctic network. The NIU is highly flexible, with its set of functions easily modified by firmware or by(More)
Hardware designers are facing new challenges in the design of complex ASIC's and processors as their sizes approach up to 100 million logic gates. We believe no adequate solution exists that allows designers to specify hardware which takes full advantage of the available resources in these devices. The hardware design specification languages are either too(More)
This thesis provides a detailed description of an ASIC I have implemented for the StarT-Voyager multi-processor. The ASIC contains the control logic of an adapter we have designed to connect SMPs into a cluster of workstations. The control logic is one of the central components of the StarT-Voyager multi-processor, a system that aims to be fast, scalable,(More)
Introduction: Past work in our group has shown that atomic actions formulated as a Term Rewriting System (TRS) are a good way to describe hardware. We have shown that advanced architectures can be described precisely using sets of atomic actions[1, 2] and formal methods can be applied to these descriptions to reason about their properties[3]. Furthermore,(More)