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Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore , results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an(More)
—Modelling at the Electronic System Level (ESL) is the established approach of the major System-on-chip (SoC) companies. While in the past ESL design covered design method-ologies only, today also verification and debugging is included. To improve the verification process, testbench automation has been introduced highlighted as constraint-based random(More)
We present an integrated system design environment for SystemC, called SyCE. The system consists of several components for efficient analysis, verification and debugging of SystemC designs. The core tools are 1) ParSyC, a parser for SystemC designs that has also some synthesis options, 2) CheckSyC, a verification tool for formal equivalence checking ,(More)
Synthesis of reversible logic has become a very important research area. In recent years several algorithms – heuristic as well as exact ones – have been introduced in this area. Typically, they use the specification of a reversible function in terms of a truth table as input. Here, the position of the outputs are fixed. However, in general it is irrelevant(More)
Determining the equivalence of reversible circuits designed to meet a common specification is considered. The circuits' primary inputs and outputs must be in pure logic states but the circuits may include elementary quantum gates in addition to reversible logic gates. The specification can include don't-cares arising from constant inputs, garbage outputs,(More)
Intensive research is performed to find post-CMOS technologies. A very promising direction based on reversible logic are quantum computers. While in the domain of reversible logic synthesis, testing, and verification have been investigated, debugging of reversible circuits has not yet been considered. The goal of debugging is to determine gates of an(More)
Due to high computational costs of formal verification on pure Boolean level, proof techniques on the word level, like Satisfiability Modulo Theories (SMT), were proposed. Verification methods originally based on Boolean satisfiability (SAT) can directly benefit from this progress. In this work we present the word level framework WoLFram that enables the(More)