Danghui Wang

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The write operation asymmetry of many memory technologies causes different write failure rates at 0 → 1 and 1 → 0 bit-flipping's. Conventional error correction codes (ECCs) spend the same efforts on both bit-flipping directions, leading to very unbalanced write reliability enchantment over different bit-flipping distributions of codewords (i.e.,(More)
As massive multi-threading in GPU imposes tremendous pressure on memory subsystems, efficient bandwidth utilization becomes a key factor affecting the GPU throughput. In this work, we propose <i>thread batch enabled memory partitioning</i> (TEMP), to improve GPU performance through the improvement of memory bandwidth utilization. In particular, TEMP(More)
The recent research reveals that the bit error rate of a NAND flash cell is highly dependent on the stored data patterns. In this work, we propose Data Pattern Aware (DPA) error protection technique to extend the lifespan of NAND flash based storage systems (NFSS). DPA manipulates the ratio of 1's and 0's in the stored data to minimize occurrence of the(More)
Spin Transfer Torque Magnetoresistive RAM (STT-MRAM) has been recently deemed as one promising main memory alternative for high-end mobile processors. With process technology scaling, the amplitude of write current approaches that of read current in deep sub-micrometer STT-MRAM arrays. As a result, read disturbance errors (RDEs) emerge. Both high current(More)
LDPC code is introduced in NAND flash memory to handle high BER (bit error rate) incurred by technology scaling. Despite strong error correction capability, LDPC decoding induces long NAND flash read latency. In this work, we propose FlexLevel -- a robust NAND flash storage system design to improve data reliability and read efficiency affected by the LDPC(More)
In recent years, multi-level-cell (MLC) NAND flash technologies are prevailingly employed in both enterprise and consumer storage systems due to the advantages on power consumption and fabrication cost. However, short endurance and long write access time of NAND flash pose challenge for system designers. The incurred high bit error prevention cost and(More)
Aggressive technology scaling and adoption of multilevel-cell technique lead to progressive increase of bit error rate (BER) of NAND flash memory. Consequently, conventional error correction code is not adequate to guarantee system reliability. As an alternative, low density parity check (LDPC) code is introduced to provide more powerful error correction(More)
Density-functional theory calculations are performed to investigate the effects of surface modifications and nanosheet thickness on the electronic and magnetic properties of gallium nitride (GaN) nanosheets (NSs). Unlike the bare GaN NSs terminating with polar surfaces, the systems with hydrogenated Ga (H-GaN), fluorinated Ga (F-GaN), and chlorinated Ga(More)