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Protecting a high performance radiation hardened by design (RHBD) cache from single-event transient (SET) induced peripheral circuit errors is presented. Cache memory holds processor architectural state and peripheral errors can cause incorrect operations that affect entire data words, including parity. Thus, a periphery circuit, e.g., word-line, error can(More)
i ABSTRACT Ever reducing time to market, along with short product lifetimes, has created a need to shorten the microprocessor design time. Verification of the design and its analysis are two major components of this design cycle. Design validation techniques can be broadly classified into two major categories: simulation based approaches and formal(More)
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