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The graphics accelerator (GRAAL) design-exploration framework is an open system that offers a coherent development methodology for hardware/software cosimulation and codesign of embedded 3D graphics accelerators. GRAAL incorporates tools to help visually debug graphics algorithms implemented in hardware and to estimate performance in terms of throughput,(More)
This paper focuses on the challenging aspects of developing a versatile hardware/software co-design and co-simulation environment for the development of 3D graphics hardware accelerators in ARM-based system-on-chip designs. The tool we propose integrates the ARMulator, the cycle-accurate instruction-level simulator for the ARM lowpower processor family,(More)
This paper presents a versatile hardware/software cosimulation and co-design environment for embedded 3D graphics accelerators. The GRAphics AcceLerator design exploration framework (GRAAL) is an open system which offers a coherent development methodology based on an extensive library of SystemC RTL models of graphics pipeline components. GRAAL incorporates(More)
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gatelevel techniques offer power savings of a factor of two or less, architecture and system-level optimization can often result in orders of magnitude lower power consumption. Therefore, the(More)
An efficient logic-enhanced memory architecture is presented that solves existing problems associated with 3D graphics tile-based hardware rasterization algorithms. The memory contains the same number of bits as the number of pixels in the tile, and during rasterization time it is filled up in several clock cycles by a systolic primitive scanconversion(More)
In recent years, power consumption has become a critical concern for many VLSI systems. Whereas several case studies demonstrate that technology-, layout-, and gate-level techniques offer power savings of a factor of two or less, architecture and system-level optimization can often result in orders of magnitude lower power consumption. Therefore, the(More)
This paper addresses design trade-offs for lowpower, low-cost embedded 3D graphics accelerators. More in particular it focuses on a low-cost reciprocation hardware algorithm suitable to be implemented in their datapath. The algorithm exploits the limitations of the human visual system that allows a reasonable amount of error to be introduced in the(More)
An efficient low-cost, low-power hardware implementation of a novel run-time pixel coverage mask generation algorithm for embedded 3D graphics antialiasing purposes is presented. The proposed algorithm can be incorporated in any antialiasing scheme with prefiltering that is based on algebraic representation of primitive's edges. When compared with the state(More)
Abstract— A 3D graphics systolic scan-conversion unit is presented that solves existing problems associated with tile-based hardware rasterization algorithms. In our proposal no searching overhead is needed to find the first hit position inside the primitives. Furthermore “ghost” primitives are handled efficiently with a small constant delay irrespective of(More)