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—This paper presents a methodology for procedural layout-aware design for nanometric technologies. A Python-based layout generation tool generates different layout styles for the same basic analog building blocks. Moreover, layout dependent parasitic parameters such as stress effects are easily computed and compared for different layout styles. The… (More)
This paper studies the matching and the stress effect problems that appear in deep submicron CMOS technologies. These effects significantly affect the electrical behavior of CMOS transistors. We propose a method to compute stress effect parameters resulting from different layout styles such as interdigitated and symmetrical styles. We apply this method to a… (More)
In this paper, a new method for developing smart parameterized generators for analogue devices is presented. A device is an atomic analogue cell that performs an elementary and standard function such as the differential pair and the current mirror. A device is smart since it can be electrically and physically adapted. In the proposed method, the device… (More)
— This paper presents a python based analog layout generation tool for nanometer CMOS technologies. To demonstrate the ease of use and extension of this tool, the paper presents how to automatically compute and plot stress effect parameters for two layout techniques of a differential pair device (interdigited and symmetric).
— In this paper, we present a nanometric layout generation tool for analogue building blocks called devices. We focus on the procedural routing methods inside devices. A device may have one or more folded transistors' fingers merged into at least one stack depending on the chosen layout style. We present two routing methods: intra-stack and inter-stack to… (More)