Damian Dalton

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This paper presents a hardware acceleration system based on a gate-level accelerator and an on-chip microprocessor enabling co-simulation of C-models with gate-level modules on the accelerator. This solution tackles the communication bottleneck that occurs when using hardware accelerators or emulators to speed up simulation. We analyze this bottleneck for(More)
  • D. Dalton
  • CompEuro 1992 Proceedings Computer Systems and…
  • 1992
Presents a parallel processing approach to logic simulation, called APPLES, in which gate evaluations and signal updating are executed in parallel in associative memory, rather than in the processor. This approach does not require any event scheduling mechanism and can model various logic gate types and delay models. Two concepts are coupled together to(More)
For developing parallel systems composed of hard- and software, powerful simulation tools are needed in order to decrease time-to-market. With the generic simulation framework, clock-cycle accurate simulation for parallel devices communicating with each other is possible. This tool is designed to support different model techniques at various levels of(More)