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A family of embedded DRAMs which are fabricated in 45nm SOI technology is presented. The fast eDRAM has 64 b/BL and achieves a random cycle time of 1.3ns for V<inf>DD</inf> = 1.00V and typical process. The dense eDRAM has 128 b/BL and operates in multi-bank modes up to 1.67GHz for V<inf>DD</inf> = 1.0V and nominal process. The staggered - folded BL(More)
An embedded DRAM macro fabricated in 65 nm CMOS achieves 1.0 GHz multi-banked operation at 1.0 V yielding 584 Gbits/sec. The array utilizes a 0.1 1 mum<sup>2</sup> cell with 20 fF deep trench capacitor and 2.2 nm gate oxide transfer gate. Concurrent refresh allows for high availability via a second bank address. At-speed test and repair is accomplished with(More)
During the 14 July 2005 encounter of Cassini with Enceladus, the Cassini Plasma Spectrometer measured strong deflections in the corotating ion flow, commencing at least 27 Enceladus radii (27 x 252.1 kilometers) from Enceladus. The Cassini Radio and Plasma Wave Science instrument inferred little plasma density increase near Enceladus. These data are(More)
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