Daksh Lehther

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Clock distribution design for high performance microprocessors has become increasingly challenging in recent years. Design goals of state-of-the-art integrated circuits, dictate the need for clock networks with smaller skew tolerances, large sizes, and lower capacitances. In this paper we discuss some of the issues in clock network design that arise in this(More)
While designing interconnect for MCM's, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are(More)
This paper describes a mixed mode chip level extraction flow deployed in high performance microprocessor designs. Two extractors of different accuracy levels are integrated to achieve best trade-off between run-time and precision. The goal is to provide sufficient accuracy at different design stages and achieve minimum extraction time possible. Three(More)
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