Dajiang Zhou

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In the latest draft video compression standard, HEVC, a new 8-tap MC interpolation filter is adopted. For this component, we propose an efficient VLSI design which is composed of a reconfigurable filter, an optimized pipeline engine organization, and a filter reuse scheme. This results in 30% area saving from a non-optimized design. The proposed(More)
H.264 and AVS are the two latest video coding standards. Since the similarity between their structures, it is feasible to develop a dual-mode VLSI decoder for supporting both standards, with substantially less cost than the solution with two individual decoders. In this paper, we propose a dualstandard VLSI architecture for MC interpolation, which is the(More)
HEVC achieves a better coding efficiency relative to prior standards, but also involves dramatically increased complexity. The complexity increase for intra prediction is especially intensive due to a highly flexible quad-tree coding structure and a large number of prediction modes. The encoder employs rate-distortion optimization (RDO) to select the(More)
HEVC achieves a better coding efficiency relative to prior standards, but also involves increased complexity. For intra prediction, complexity is especially intensive due to a highly flexible coding unit structure and a large number of prediction modes. This paper presents a low-complexity intra prediction algorithm for HEVC. A fast preprocessing stage(More)
The up-coming video compression standard, high efficiency video coding (HEVC), reduces 50% bit rates in encoding video sequences with same picture quality compared to H.264/AVC. In the in-loop filter (LF) part of HEVC, sample adaptive offset (SAO) is newly added and de-blocking filter (DBF) has been changed a lot. Thus how to construct a high speed and low(More)
The High Efficiency Video Coding (HEVC), as the new standard of video coding, provides significantly better coding efficiency than all existing video coding standards. One key contributor to this improvement is the new intra prediction method that supports a large number of prediction directions in the quad-tree structure. It takes a very high cost of(More)
Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real-time processing capability. In this paper, we present a VLSI implementation of FME design in High Efficiency Video Coding (HEVC) for ultra-high definition video (Ultra-HD) applications. We firstly propose a(More)