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An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology

• Tetsuro Matsuno, Daisuke Fujimoto, +4 authors Makoto Nagata
• IEICE Transactions
• 2010

Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits

• Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata
• IEICE Transactions
• 2010

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design

• Daisuke Kosaka, Yoji Bando, +4 authors Makoto Nagata
• 2009 IEEE Custom Integrated Circuits Conference
• 2009

A fully integrated framework of full-chip power and substrate noise analysis is discussed, featuring description of transistor-level custom circuits as dynamic noise sources, a high capacity solver… (More)

Chip-Level Substrate Coupling Analysis with Reference Structures for Verification

• Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
• IEICE Transactions
• 2007

Chip-level substrate coupling analysis uses F-matrix computation with slice-and-stack execution to include highly concentrated substrate resistivity gradient. The technique that has been applied to… (More)

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation

• Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
• 2007 IEEE Custom Integrated Circuits Conference
• 2007

Slice-and-stack representation of a vertical substrate impurity profile in F-matrix computation captures isolation effects of deep N-wells as well as guard rings in chip-level substrate coupling. A… (More)

Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation

• Daisuke Kosaka, Makoto Nagata
• Asia and South Pacific Conference on Design…
• 2006

A substrate-coupling equivalent circuit can be derived for an arbitrary guard ring test structure by way of F-matrix computation. The derived netlist represents a unified impedance network among… (More)

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology

• Tetsuro Matsuno, Daisuke Fujimoto, +4 authors Makoto Nagata
• 2009 IEEE Custom Integrated Circuits Conference
• 2009

An arbitrary noise generator (ANG) is based on time-series charging of divided parasitic capacitance (TSDPC) and emulates power supply noise generation in a CMOS digital circuit. A prototype ANG… (More)

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits

• Daisuke Kosaka, Makoto Nagata, Yoshitaka Murasaka, Atsushi Iwata
• IEICE Transactions
• 2007

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