Daisaburo Takashima

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A 64-Mb chain ferroelectric RAM (chainFeRAM) is fabricated using 130-nm 3-metal CMOS technology. A newly developed quad bitline architecture, which combines folded bitline configuration with shield bitline scheme, eliminates bitline-bitline (BL-BL) coupling noise. The quad bitline architecture also reduces the number of sense amplifiers and activated(More)
Difficulty to achieve high density FeRAMs with sub-micron ferroelectric capacitors is widely understood due to damage to the capacitors. Key process techniques such as high quality ferroelectric film deposition, electrode preparation, capacitor RIE and hydrogen barrier structure formation are introduced for 64M FeRAMs with sub micron high reliability PZT(More)
A ferroelectric capacitor overdrive technique with shield-bitline drive has been demonstrated and verified by a 130 nm 576 Kb test chip with a 0.7191 m cell. First, cell signal degradation and bitline-to-bitline coupling noise worsened by wide cell signal distribution in low voltage scaled FeRAMs are discussed. Next, the shield-bitline-overdrive technique(More)
Using New Technologies in Post Scaling Era Jim Kahle, IBM, Austin, TX New approaches to Innovation will be required as standard CMOS scaling slows. A number of promising technologies such as storage class memory and 3D stacked memory are appearing on the horizon. These new technologies have promising attributes for storage and memory usage and how we(More)