D. Tille

A technique that applies structural information while transforming large industrial circuits into a CNF significantly reduces the size of the SAT instances for ATPG. Expand

In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. Expand

We present a first approach to integrate a SAT-based engine into the industrial ATPG environment of NXP Semiconductors. Expand

Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Expand

We propose a SAT-based approach to calculate test patterns for the GDFM in industrial circuits containing multi-valued logic. Expand

This paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. Expand

We propose the SAT technique Dynamic Clause Activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Expand

We analyze the two steps SAT-based ATPG consists of with respect to their run time and propose an incremental solving technique with the objective to speed up the entire classification process. Expand

This work introduces a novel concept of Low- Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power regions. Expand

The influence of crosstalk noise grows as the feature sizes in modern designs decrease. Expand