• Publications
  • Influence
On Acceleration of SAT-Based ATPG for Industrial Designs
TLDR
A technique that applies structural information while transforming large industrial circuits into a CNF significantly reduces the size of the SAT instances for ATPG. Expand
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Test Pattern Generation using Boolean Proof Engines
TLDR
In Test Pattern Generation using Boolean Proof Engines, we give an introduction to ATPG. Expand
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Studies on Integrating SAT-based ATPG in an Industrial Environment
TLDR
We present a first approach to integrate a SAT-based engine into the industrial ATPG environment of NXP Semiconductors. Expand
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Incremental Solving Techniques for SAT-based ATPG
TLDR
Automatic test pattern generation (ATPG) based on Boolean satisfiability (SAT) problem has recently been proven to be a beneficial complement to traditional methods. Expand
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Experimental Studies on SAT-Based ATPG for Gate Delay Faults
TLDR
We propose a SAT-based approach to calculate test patterns for the GDFM in industrial circuits containing multi-valued logic. Expand
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A fast untestability proof for SAT-based ATPG
TLDR
This paper presents a preprocessing technique that speeds up the classification of untestable faults by accelerating the SAT instance generation. Expand
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Speeding up SAT-Based ATPG Using Dynamic Clause Activation
TLDR
We propose the SAT technique Dynamic Clause Activation (DCA) in order to reduce the run time gap between structural and SAT-based ATPG algorithms and, at the same time, retain the high level of robustness. Expand
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Incremental SAT Instance Generation for SAT-based ATPG
  • D. Tille, R. Drechsler
  • Computer Science
  • 11th IEEE Workshop on Design and Diagnostics of…
  • 16 April 2008
TLDR
We analyze the two steps SAT-based ATPG consists of with respect to their run time and propose an incremental solving technique with the objective to speed up the entire classification process. Expand
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Formal Test Point Insertion for Region-based Low-Capture-Power Compact At-Speed Scan Test
TLDR
This work introduces a novel concept of Low- Capture-Power Test Points (LCP-TPs), which are inserted to reduce switching activity in critical High-Capture-Power regions. Expand
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Efficient test generation with maximal crosstalk-induced noise using unconstrained aggressor excitation
TLDR
The influence of crosstalk noise grows as the feature sizes in modern designs decrease. Expand
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