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Yield-oriented computer-aided defect diagnosis
Any good yield-oriented defect strategy must have two main components-(a) the ability to perform rapid defect diagnosis for yield learning, and (b) the ability to efficiently extract defectExpand
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SRAM-based extraction of defect characteristics
In modern IC manufacturing, extraction of defect characteristics for yield estimation is of prime importance. Test structure based defect characterization procedures suffer from two drawbacks-wastageExpand
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Stacked 3-dimensional 6T SRAM cell with independent double gate transistors
A stacked three-dimensional six transistor SRAM cell using a novel vertical slit field effect transistor with two independently controlled gates is proposed. A compact stacked 3D memory cell topologyExpand
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Analog design challenges and trade-offs using emerging materials and devices
Analog device figures-of-merit change significantly with the introduction of advanced materials and devices such as high-k or Multiple-Gate FETs. Measurements show enhanced intrinsic gain andExpand
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Critical area analysis for design-based yield improvement of VLSI circuits
Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated forExpand
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Yield and reliability analysis of digital standard cells with resistive defects
Abstract New kinds of faults in digital ICs caused by particles with a certain resistance value are presented. By using an enhanced version of a three dimensional contamination-defect-fault simulatorExpand
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High Speed , Low Power Design Rules for SRAM Precharge and Self-timing under Technology Variations
Due to low-power and reliability requirements, supply voltage is constantly decreasing. On the other hand, high speed operation is required along with increasing memory size. In a CMOS SRAM, powerExpand
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Advances in Radio Science Circuit design with Independent Double Gate Transistors
Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. This paper introduces a novelExpand