D. Rossi

Publications232
h-index29
Citations3,165
Highly Influential Citations180
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Combining BPM and social software: contradiction or chance?
TLDR
The results of the workshop on Business Process Management and Social Software (BPMS2’08) show the manifold possibilities of joining concepts from Business Process management and social software and offers new possibilities for a more effective and flexible design of business processes. Expand
Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
TLDR
This paper describes the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters, and introduces instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy. Expand
YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
TLDR
This paper presents an accelerator optimized for binary-weight CNNs that significantly outperforms the state-of-the-art in terms of energy and area efficiency and removes the need for expensive multiplications, as well as reducing I/O bandwidth and storage. Expand
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights
TLDR
A HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a core area of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V is presented. Expand
A transprecision floating-point platform for ultra-low power computing
TLDR
A software library that enables exploration of FP types by tuning both precision and dynamic range of program variables is introduced and a methodology to integrate the library with an external tool for precision tuning is presented, and experimental results that highlight the clear benefits of introducing the new formats are presented. Expand
A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing
TLDR
This paper describes a System on Chip implementation of a reconfigurable digital signal processor that enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigured engines. Expand
Jada - Coordination and Communication for Java Agents
TLDR
This chapter introduces Jada, a coordination toolkit for Java where coordination among either concurrent threads or distributed Java objects is achieved via shared object spaces, and thinks that this technology can give its best in the field of distributed-cooperative work, both in the perspective of Internet and Intranet connectivity. Expand
GAP-8: A RISC-V SoC for AI at the Edge of the IoT
TLDR
GAP-8 is proposed: a multi-GOPS fully programmable RISC-V IoT-edge computing engine, featuring a 8-core cluster with CNN accelerator, coupled with an ultra-low power MCU with 30 μW state-retentive sleep power. Expand
Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications
TLDR
This paper introduces Zero-riscy and Micro-ris Cy, two novel RISC-V cores targeting mixed arithmetic/control applications and control-oriented tasks respectively and compares them with the DSP-enhanced open-source Riscy core. Expand
A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology
Abstract Ultra-low power operation and extreme energy efficiency are strong requirements for a number of high-growth application areas, such as E-health, Internet of Things, and wearable… Expand
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