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Combining BPM and social software: contradiction or chance?
TLDR
The results of the workshop on Business Process Management and Social Software (BPMS2'08), as part of the International Conference on Business process Management in Milano, show the manifold possibilities of combining concepts from Business Process management and social software.
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Near-Threshold RISC-V Core With DSP Extensions for Scalable IoT Endpoint Devices
TLDR
This paper describes the design of an open-source RISC-V processor core specifically designed for NT operation in tightly coupled multicore clusters, and introduces instruction extensions and microarchitectural optimizations to increase the computational density and to minimize the pressure toward the shared-memory hierarchy.
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A transprecision floating-point platform for ultra-low power computing
TLDR
A software library that enables exploration of FP types by tuning both precision and dynamic range of program variables is introduced and a methodology to integrate the library with an external tool for precision tuning is presented, and experimental results that highlight the clear benefits of introducing the new formats are presented.
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YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights
TLDR
A HW accelerator optimized for BinaryConnect CNNs that achieves 1510 GOp/s on a core area of only 1.33 MGE and with a power dissipation of 153 mW in UMC 65 nm technology at 1.2 V is presented.
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YodaNN: An Architecture for Ultralow Power Binary-Weight CNN Acceleration
TLDR
This paper presents an accelerator optimized for binary-weight CNNs that significantly outperforms the state-of-the-art in terms of energy and area efficiency and removes the need for expensive multiplications, as well as reducing I/O bandwidth and storage.
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GAP-8: A RISC-V SoC for AI at the Edge of the IoT
TLDR
GAP-8 is proposed: a multi-GOPS fully programmable RISC-V IoT-edge computing engine, featuring a 8-core cluster with CNN accelerator, coupled with an ultra-low power MCU with 30 μW state-retentive sleep power.
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PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision
TLDR
PULP (Parallel processing Ultra-Low Power platform), an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that exploit the capabilities of the STMicroelectronics UTBB FD-SOI 28nm technology is proposed.
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Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube
TLDR
The first exploration steps towards design of the Smart Memory Cube SMC are presented, a new Processor-in-Memory PIM architecture that enhances the capabilities of the logic-base LoB die in HMC and a zero-copy pointer passing mechanism has been devised to allow low overhead data sharing between the host and the PIM.
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A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing
TLDR
This paper describes a System on Chip implementation of a reconfigurable digital signal processor that enables the programmer to manage the high level synchronization and global data of complex signal processing applications through the ARM processor, while allocating most critical computational kernels to the most suitable reconfigured engines.
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Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes
TLDR
This paper proposes a flexible processor-in-memory (PIM) solution for scalable and energy-efficient execution of deep convolutional networks (ConvNets), one of the fastest-growing workloads for servers and high-end embedded systems.
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