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A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme
TLDR
In this paper we propose a dedicated architecture to implement a 2-D discrete wavelet transform computed by adopting the new lifting scheme framework. Expand
  • 41
  • 3
A scalable wide-issue clustered VLIW with a reconfigurable interconnect
TLDR
A clustered VLIW with a runtime reconfigurable inter-cluster bus suitable to address scalability problem. Expand
  • 14
  • 2
Handling borders in systolic architectures for the 1-D discrete wavelet transform for perfect reconstruction
TLDR
We propose a modified systolic architecture that implements the 1-D discrete wavelet transform (DWT) on the basis of the recursive pyramid algorithm (RPA) while correctly managing the border problem and obtaining perfect reconstruction. Expand
  • 33
  • 1
A video compression case study on a reconfigurable VLIW architecture
  • D. Rizzo, O. Colavin
  • Computer Science
  • Proceedings Design, Automation and Test in…
  • 4 March 2002
TLDR
In this paper, we investigate the benefits of a flexible, application-specific instruction set by adding a run-time Reconfigurable Functional Unit (RFU) to a VLIW processor. Expand
  • 13
  • 1
  • PDF
Benchmarking Hough Transform Architectures for Real-Time
TLDR
This paper reviews the Hough transform hardware implementations, with a specific analysis of the architectures that explicitly address the “real-time” issue. Expand
  • 12
Multimedia Extensions and Sub-word Parallelism in Image Processing: Preliminary Results
TLDR
This paper presents experimental results obtained on a very simple algorithm, the Haar transform, that has been coded for the HP and the Intel multimedia microengines. Expand
  • 5
Wavelet Transform Architectures: A System Level Review
TLDR
In this paper we review the architectures designed for wavelet transforms, with the purpose to highlight their suitability for inclusion in codee systems. Expand
  • 5
On the Synthesis of a Controller for Handling Borders in Systolic Architectures for 1-D Discrete Wavelet Transform
TLDR
In this paper we describe the control subsystem of a systolic architecture that implements the 1-D discrete wavelet transform (DWT) on the basis of the Recursive Pyramid Algorithm (RPA) and that correctly manages the border problem adopting a periodic extension strategy to obtain a perfect reconstruction of the signal. Expand
  • 1
  • PDF
Towards a VHDL-based synthesis of a wavelet transform processor
  • M. Ferretti, D. Rizzo
  • Computer Science
  • Proceedings Fourth IEEE International Workshop on…
  • 20 October 1997
TLDR
We analyze the implementation of Mallat's "pyramid" algorithm for the wavelet transform through synthesis tool (Synopsys/sup TM/ Behavioral Compiler). Expand