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  • Influence
The SGI Origin: A ccnuma Highly Scalable Server
TLDR
The motivation for building the Origin 2000 is discussed and the architecture and implementation of the multiprocessor is described, and performance results are presented for the NAS Parallel Benchmarks V2.2 and the SPLASH2 applications. Expand
Memory consistency and event ordering in scalable shared-memory multiprocessors
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced. A framework for classifying shared accessesExpand
The Stanford Dash multiprocessor
TLDR
The overall goals and major features of the directory architecture for shared memory (Dash), a distributed directory-based protocol that provides cache coherence without compromising scalability, are presented. Expand
Memory consistency and event ordering in scalable shared-memory multiprocessors
TLDR
A new model of memory consistency, called release consistency, that allows for more buffering and pipelining than previously proposed models is introduced and is shown to be equivalent to the sequential consistency model for parallel programs with sufficient synchronization. Expand
The directory-based cache coherence protocol for the DASH multiprocessor
TLDR
The design of the DASH coherence protocol is presented and how it addresses the issues of correctness, performance and protocol complexity are discussed and compared to the IEEE Scalable Coherent Interface protocol. Expand
The DASH Prototype: Logic Overhead and Performance
TLDR
The fundamental premise behind the DASH project is that it is feasible to build large-scale shared-memory multiprocessors with hardware cache coherence with a small cost for the ease of programming offered by coherent caches and the potential for higher performance. Expand
The DASH prototype: implementation and performance
TLDR
The hardware overhead of directory-based cache coherence in the prototype of the DASH multiprocessor is examined and the effectiveness of coherent caches and the relationship between an application's reference behavior and its speedup is characterized. Expand
The directory-based cache coherence protocol for the DASH multiprocessor
TLDR
The design of the DASH coherence protocol is presented and discussed from the viewpoint of how it addresses the issues of correctness, performance, and protocol complexity. Expand
Scalable Shared-Memory Multiprocessing
TLDR
The aim of this presentation is to provide a discussion of the design and implementation of Scalable Shared-Memory Systems, as well as some of the techniques used to design and implement these systems. Expand
Design of scalable shared-memory multiprocessors: the DASH approach
The DASH (directory architecture for shared-memory) multiprocessor, which combines the programmability of shared-memory machines with the scalability of message-passing machines, is described.Expand
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