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Transactional Locking II
This paper introduces the transactional locking II (TL2) algorithm, a software transactional memory (STM) algorithm based on a combination of commit-time locking and a novel global version-clock based validation technique, which is ten-fold faster than a single lock.
Early experience with a commercial hardware transactional memory implementation
The experience includes a number of promising results using HTM to improve performance in a variety of contexts, and also identifies some ways in which the feature could be improved to make it even better.
Transactional Mutex Locks
- Luke Dalessandro, D. Dice, M. Scott, N. Shavit, Michael F. Spear
- Computer ScienceEuro-Par
- 31 August 2010
Using optimized spinlocks and the TL2 STM algorithm as baselines, TML provides the low latency of locks at low thread levels, and the scalability of STM for read-dominated workloads, suggesting that TML is a good reference implementation to use when evaluating STM algorithms.
Lock cohorting: a general technique for designing NUMA locks
This paper presents lock cohorting, a general new technique for designing NUMA-aware locks that is as simple as it is powerful, and allows one to transform any spin-lock algorithm, with minimal non-intrusive changes, into scalable NUma-aware spin-locks.
TLRW: return of the read-write lock
This paper makes the claim that the cost of coherence in such single chip systems is down to a level that allows one to design a scalable STM based on read-write locks, and introduces TLRW, a new STM algorithm intended for the single-chip multicore systems.
This article presents lock cohorting, a general new technique for designing NUMA-aware locks that is as simple as it is powerful, and allows one to transform any spin-lock algorithm, with minimal nonintrusive changes, into a scalable NUma-aware spin-locks.
NUMA-aware reader-writer locks
- I. Calciu, D. Dice, Yossi Lev, Victor Luchangco, Virendra J. Marathe, N. Shavit
- Computer SciencePPoPP '13
- 23 February 2013
This paper presents what is, to the best of the knowledge, the first family of reader-writer lock algorithms tailored to NUMA architectures, and presents several variations which trade fairness between readers and writers for higher concurrency among readers and better back-to-back batching of writers from the same N UMA node.
What Really Makes Transactions Faster
It is found that it was the lower latency of the hand-crafted data structures that made them faster than STMs, and not better contention management or optimizations based on the programmer’s understanding of the particulars of the structure.
Understanding Tradeoffs in Software Transactional Memory
This paper created the transactional locking (TL) framework of STM algorithms and used it to conduct a range of comparisons of the performance of non-blocking, lock-based, and Hybrid STm algorithms versus fine-grained hand-crafted ones.
Compact NUMA-aware Locks
This work presents a compact NUMA-aware lock that requires only one word of memory, regardless of the number of sockets in the underlying machine, and implemented the new lock in user-space as well as integrated it in the Linux kernel's qspinlock, one of the major synchronization constructs in the kernel.