• Publications
  • Influence
Lock-free Transactions without Rollbacks for Linked Data Structures
TLDR
We present a new methodology for transforming high-performance lock-free linked data structures into high- performance lock- free transactional linkeddata structures without revamping the data structures' original synchronization design. Expand
  • 26
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Lock-Free Dynamically Resizable Arrays
TLDR
We present a first lock-free design and implementation of a dynamically resizable array (vector). Expand
  • 58
  • 2
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A Lock-Free Priority Queue Design Based on Multi-Dimensional Linked Lists
  • D. Zhang, D. Dechev
  • Computer Science
  • IEEE Transactions on Parallel and Distributed…
  • 1 March 2016
TLDR
We present a quiescently consistent lock-free priority queue based on a multi-dimensional list that guarantees worst-case search time of O(logN) for key universe of size N. Expand
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A Wait-Free Multi-Word Compare-and-Swap Operation
TLDR
The number of cores in future multi-core systems are expected to increase by 100 fold over the next decade. Expand
  • 18
  • 1
An Efficient Wait-Free Vector
TLDR
We present a new resize algorithm which facilitates concurrent access and modification during resize, allowing the use of a contiguous memory model. Expand
  • 14
  • 1
The ABA problem in multicore data structures with collaborating operations
  • D. Dechev
  • Computer Science
  • 7th International Conference on Collaborative…
  • 1 October 2011
TLDR
An increasing number of modern real-time systems and the nowadays ubiquitous multicore architectures demand the application of programming techniques for reliable and efficient concurrent synchronization. Expand
  • 10
  • 1
Scalable nonblocking concurrent objects for mission critical code
TLDR
The high degree of complexity and autonomy of future robotic space missions, such as Mars Science Laboratory (MSL), poses serious challenges in assuring their reliability and efficiency. Expand
  • 10
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Designing digital circuits for FPGAs using parallel genetic algorithms (WIP)
TLDR
In this paper, parallel GA algorithms are proposed for the synthesis of digital circuits for LUT-based FPGA architectures based on Genetic Algorithms. Expand
  • 9
  • 1
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Check-Wait-Pounce: Increasing Transactional Data Structure Throughput by Delaying Transactions
TLDR
Check-Wait-Pounce improves upon existing methodologies by delaying the execution of transactions until they are expected to succeed, using a thread-unsafe representation of the data structure as a heuristic. Expand
  • 2
  • 1
Using SST/Macro for Effective Analysis of MPI-Based Applications: Evaluating Large-Scale Genomic Sequence Search
TLDR
A simulation-based framework for analyzing the scalability and performance of a number of critical optimizations of a massively parallel genomic search application, mpiBLAST, using an advanced macroscale simulator (SST/macro). Expand
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