• Publications
  • Influence
Formal online methods for voltage/frequency control in multiple clock domain microprocessors
TLDR
This paper presents an effective online DVFS scheme for an MCD processor which takes a formal analytic approach, is driven by dynamic workloads, and is suitable for all applications and can be generalized for energy control in processors other than MCD, such as tiled stream processors. Expand
A dynamic compilation framework for controlling microprocessor energy and performance
TLDR
While the proposed technique is an effective method for microprocessor voltage and frequency control, the design framework and methodology described in this paper have broader potential to address other energy and power issues such as di/dt and thermal control. Expand
Performance of the VAX-11/780 translation buffer: simulation and measurement
TLDR
The authors present the results of a set of measurements and simulations of translation buffer performance in the VAX-11/780, a hardware cache of recently used virtual-to-physical address mappings. Expand
Building and Using A Scalable Display Wall System
TLDR
The approach to research challenges in several specific research areas, including seamless tiling, parallel rendering, parallel data visualization, parallel MPEG decoding, layered multiresolution video input, multichannel immersive sound, user interfaces, application tools, and content creation are described. Expand
Improving prediction for procedure returns with return-address-stack repair mechanisms
TLDR
For conventional, single-path processors, this paper proposes saving both the top-of-stack pointer and the top of-stack contents for later restoration in case of a misprediction, which achieves nearly 100% hit rates and improves performance by up to 8.7% compared to a stack with no repair mechanism. Expand
Design issues and tradeoffs for write buffers
  • K. Skadron, D. Clark
  • Computer Science
  • Proceedings Third International Symposium on High…
  • 1 February 1997
TLDR
This paper uses instruction level simulation of SPEC92 benchmarks to investigate how different write buffer depths, retirement policies, and load-hazard policies affect these three types of write-buffer stalls. Expand
Formal control techniques for power-performance management
TLDR
Using dynamic voltage and frequency scaling to balance speed and avoid worst case frequency limitations for both multiple-clock-domain and chip multiprocessors. Expand
Cache Performance in the VAX-11/780
  • D. Clark
  • Computer Science
  • TOCS
  • 1 February 1983
TLDR
Measurements are reported including the hit ratios of data and instruction references, the rate of cache invalidations by I/O, and the amount of waiting time due to cache misses. Expand
The performance impact of incomplete bypassing in processor pipelines
TLDR
In this paper bypassing is studied in detail, with an emphasis on designs in which the bypassing network is not complete, and two types of code alterations reduce the new interlock stalls. Expand
Coordinated, distributed, formal energy management of chip multiprocessors
TLDR
This paper illustrates how the use of local, per-tile dynamic voltage and frequency scaling (DVFS) techniques can result in tiles counteracting each others' power management policies, significantly hurting chip power-performance, and proposes a coordinated DVFS scheme for CMPs, which eliminates the oscillations and ensures efficient and resilient DVFS control. Expand
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