D. Bhandarkar

Publications21
h-index9
Citations1,767
Highly Influential Citations77
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IEEE Standard for Floating-Point Arithmetic
Performance characterization of the Pentium Pro processor
  • D. Bhandarkar, J. Ding
  • Computer Science
    Proceedings Third International Symposium on High…
  • 1 February 1997
TLDR
The Pentium Pro processor achieves significantly lower cycles per instruction than the Pentium processor due to its out of order and speculative execution, and non-blocking cache and memory system.
Characterization of alpha AXP performance using TP and SPEC workloads
TLDR
A simple model for evaluating the effects of various design tradeoffs based on the data collected by using hardware monitors is proposed and indicates that Alpha AXP takes advantage of lower cycles per instruction and cycle time to achieve a significant performance advantage.
Performance from architecture: comparing a RISC and a CISC with similar hardware organization
TLDR
This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks and demonstrates the correlation between cycles per instruction and relative instruction count.
An American National Standard- IEEE Standard for Binary Floating-Point Arithmetic
Performance characterization of the Alpha 21164 microprocessor using TP and SPEC workloads
TLDR
The AlphaServer 8200 provides 2 to 3 times the performance of the DEC 7000 server based on the faster clock, larger on-chip cache, expanded multiple-issuing, and lower cache/memory latencies and higher bandwidth.
Alpha implementations and architecture - complete reference and guide
Historical perspective RISC design issues Alpha architecture comparing RISC architectures first generation Alpha processor chips 21064-based system implementations second generation microprocessor…
RISC versus CISC: a tale of two chips
TLDR
An aggressive RISC and CISC implementation built with comparable technology and using performance counter statistics to compare various aspects of both designs is compared.
Vector extensions to the VAX architecture
TLDR
The extension of the VAX architecture to include integrated vector processing is discussed and the architecture maximizes the asynchronism between the scalar and vector processors and the parallelism within the vector processor.
VAX vector architecture
The VAX Architecture has been extended to include an integrated, register-based vector processor. This extension allows both high-end and low-end implementations and can be supported with only small…
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