D. T. Wisland

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We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device(More)
A novel CMOS impulse radar for CMOS implementation is proposed exploring the concept of swept-threshold sampling. Time-domain signal processing with counter-based integration in parallel structures is used. With continuous time delay line based parallel sampling topologies we achieve a sampling rate in excess of 20GHz. A functional CMOS impulse radar is(More)
This paper describes a multi-bit ΔΣ FM-to-digital converter (FDC) combining 1024 first-order AE modulators in parallel to increase the signal to quantization-noise ratio (SQNR). This parallelization technique is totally new and according to theory, the SQNR is increased by 6 dB per doubling of number of modulators. The proposed circuit is an(More)
Ultra wideband systems are hard to implement in standard CMOS technology. In this paper we present a novel spatial RAKE-receiver, exploring mixed-mode circuits for symbol detection and inverter delay lines for synchronization. The receiver is implemented as a RAKE structure combining digital shift registers with analog computation in a series of parallel(More)
A low-voltage, low-power, and wide-tuning-range VCO which converts an analog input voltage to phase information for a frequency ΔΣ modulator is proposed in this paper. The VCO is based on a differential ring oscillator, which is improved with modified symmetric load and a positive feedback in the differential delay cells, a new bias circuit(More)
In this paper a new full adder (FA) circuit optimized for ultra low power operation is proposed. The circuit is based on modified XOR gates operated in the subthreshold region to minimize the power consumption. Simulated results using 65 nm standarad CMOS models are provided. The simulation results show a 5%-20% for frequency ranges from 1 KHz to 20 MHz and(More)
This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared with latter proposed circuit. According to simulations in a predictive(More)
Low power-impulse radio receiver front ends are hard to implement in standard CMOS. In this paper we present a simple thresholding solution exploring simple inverter structures. The ultra wide band impulse radio receiver front end consists of a LNA, integrator and thresholding pulse shaper all in standard digital CMOS technology. The continuous time(More)
This paper describes a fully integrated CMOS-MEMS pressure sensor implemented in a standard 0.6 /spl mu/m process from AMS. The fabricated chip includes all necessary components from pressure sensor to A/D-converter and decimation filter. The pressure sensitive diaphragm is fabricated using one single postprocessing step. Theoretical background is provided(More)
The application of microelectromechanical systems (MEMS) is currently growing, increasing the demands for efficient interfacing between the MEMS sensor and CMOS interfacing circuitry. This paper presents a fully integrated CMOS-MEMS pressure sensor, including a frequency-to-digital converter on the same CMOS die. The main purpose of this work is to explore(More)