D. Soudris

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A systematic approach for mapping of iterative algorithms into fault-tolerant processor arrays is presented. The initial description of the algorithms is Fortran-like nested loops, and the restrictions of the intermediate forms such as UREs are avoided. The principles of the coordinate method are used and regular or piecewise regular arrays can be derived.(More)
Existing application domains exhibit variations in terms of complexity, performance and power consumption, whereas their efficient implementation onto general-purpose FPGAs is not always a viable solution. In this paper we introduce a framework for designing self-aware reconfigurable platforms. Rather than similar approaches, our solution having a template(More)
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