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  • D. Le
  • ACM Trans. Math. Softw.
  • 1985
An algorithm is presented for finding a root of a real function. The algorithm combines bisection with second and third order methods using derivatives estimated from objective function values. Globaql convergence is ensured and the number of function evaluations is bounded by four times the number needed by bisection. Numerical comparisons with existing(More)
The form factor of mobile devices and their associated thermal dissipation characteristics present practical limits to SoC (and specifically CPU) power consumption. Multiple maximum temperature constraints interact with the thermal “time constant” of package and product to limit allowable die temperature. This can constrain maximum CPU frequency in real use(More)
The techniques proposed in the previous deliverable D4.1 [8] for synchronization, channel estimation and equalization in FBMC, are now completed and some additional results presented. The MIMO techniques for multiantenna radiocommunication systems have been analyzed and adapted to the FBMC context and new space diversity and multiplexing algorithms have(More)
An electrical and physical design power optimization methodology and design techniques developed to create an ARM 1136SF-S microprocessor in 9Onm standard CMOS are presented. A 40% reduction in power dissipation has been achieved while maintaining a 355 MHz operating clock rate under typical conditions. Functional and electrical design requirements were(More)
A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. /spl sim/76M(More)
A system-centric, fully-hierarchical design methodology and design techniques developed to create four ICs, which provide the core functionality of a multi-Gigabit switching network system, are presented. The system is capable of switching more than 500 million packets per second. Electrical and physical design methods for one IC are described. /spl sim/76(More)
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