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Journals and Conferences
A single-chip VLSI (very large-scale integration) echo canceler has been fabricated in NMOS(N-channel metal-oxide semiconductor). The canceler has a 128-tap (16-ms) delay line and a white-noise convergence rate of 70 dB/s. The chip measures 313 by 356 mils and contains 35,000 devices.
Phase comparators used in phase-locked loops extracting symbol timing from baseband data waveforms typically only produce a useful error signal when a data transition occurs. This gating of the error signal by data transitions makes the natural model for studying jitter in such phase-locked loops time-varying and difficult to analyze. In this paper we show… (More)
A single-chip VLSI echo canceler fabricated in 5μ Si-gate enhancement NMOS technology will be discussed. The chip, containing 2704 bits of dynamic shift register and 3300 logic gates, measures 313 × 356 mils.
Describes how annoying echoes in two-way conversations via satellite are eliminated by using an inexpensive silicon circuit which is an IC containing more than 30000 transistors.