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This paper presents a high speed low power digital multiplier by taking the advantage of Vedic multiplication algorithms with a very efficient leakage control technique called McCMOS technology. We have designed a 8 bit Vedic multiplier using Multiple channel CMOS (McCMOS) technology, by using 130 nm, 90 nm, 65 nm & 45 nm node technology and presents(More)
This paper proposes an efficient design technique of high performance linear convolution of two finite length sequences using Multiple Channel CMOS technique. McCMOS technique uses non-minimum length transistors which offer the possibility of achieving excellent leakage control in nano-scale CMOS design with a very modest increase in area and switched(More)
Abstract:Optimization of SRAM (Static Random Access Memory) array design can be done at three domains namely bit cell optimization, sense amplifier optimization and memory decoder optimization. In this paper, we focused on memory decoder optimization. The objective of the paper is to design speed and power efficient memory decoder structure and to implement(More)
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