D. A. Yokoyama-Martin

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A binary backplane transceiver core in 0.13-/spl mu/m dual-gate low-voltage (LV) CMOS, operating at 0.6-9.6 Gb/s with an area of 0.56 mm/sup 2/, is presented. The core uses two taps of transmit preemphasis and an adaptive receive equalization strategy incorporating one tap of unrolled decision feedback equalization (DFE), a linear equalizer, and a bandwidth(More)
A backplane transceiver core in 0.13 /spl mu/m dual-gate CMOS, operating at 0.6 to 9.6 Gb/s with an area of 0.56 mm/sup 2/ and dissipating 150 mW at 6.25 Gb/s, is presented. This core uses a unique adaptive receive equalization strategy, transmit pre-emphasis, and has extensive optional test features including a built-in BER tester and an on-chip receiver(More)
A low power, small area transceiver PHY that supports PCIetrade, SATA II, and XAUI was fabricated in TSMC's 90nm dual gate CMOS. Each lane occupies an area of 400mum times 430mum. Operation also requires a clock module of 400mum times 430mum. A 4-lane, wirebond testchip consumes 195mW of power at 3.125Gb/s. The paper focuses on the analog sections of the(More)
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