Cyprian Uzoh

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We present the first fully integrated ULSI CMOS/copper interconnect technology. Up to 6 Cu wiring levels are built at minimum metal-contacted pitch of 0.63 /spl mu/m, with W local-interconnect and contact levels and a polycontacted pitch of 0.81 /spl mu/m, on a fully-scaled sub 0.25 /spl mu/m, 1.8 V CMOS technology. The Cu wiring has advantages of(More)
This paper presents spiral inductor structures optimized in a Cu-damascene VLSI interconnect technology with use of silicon, high-resistivity silicon (HRS), or sapphire substrates. Quality factors (Q) of 40 at 5.8 GHz for a 1.4 nH-inductor and 13 at 600 MHz for a 80 nH-inductor have been achieved.
Glomerulomegaly is a histologic finding present in idiopathic pulmonary hypertension, congenital cyanotic heart disease, morbid obesity associated with sleep apnea syndrome, sickle cell disease, and polycythemic states. This study examines the case of a 34-yr-old woman with idiopathic pulmonary artery hypertension who presented with nephrotic-range(More)
This paper presents Invensas' silicon interposer technology for heterogeneous chip integration. Various process module and integrated blocks were optimized for yield and high performance in the interposer. The modules under evaluation include TSV etch, barrier deposition, electrochemical plating, chemical mechanical polishing (CMP), temporary bonding, low(More)
The 3D-IC stacking technology provides improved performance, and reduced form factor for applications such as logic-memory integration, image sensors, MEMS, and LED. We present design and fabrication methods to implement Through Silicon Via (TSV) interposer. Cylindrical copper TSV’s of 20 μm diameter and 100 μm depth are fabricated in silicon. We present a(More)
Damascene Cu electroplating for on-chip metallization, which we conceived and developed in the early 199Os, has been central to IBM's Cu chip interconnection technology. We review here the challenges of filling trenches and vias with Cu without creating a void or seam, and the discovery that electrodeposition can be engineered to give filling performance(More)
Leading-edge technology integration, high-bandwidth and low-power data access call for vertical stacking of semiconductor devices with very fine pitch interconnects. To address this demand, a unique technology referred to as Direct Bond Interconnect (DBI®) which was invented by Ziptronix [1] is being further developed for die to wafer applications.(More)
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