Filter Results:
- Full text PDF available (2)
Publication Year
2004
2009
- This year (0)
- Last 5 years (0)
- Last 10 years (1)
Publication Type
Co-author
Journals and Conferences
Learn More
- Jia Zeng, Cristian Soviani, Stephen A. Edwards
- LCTES
- 2004
While concurrency in embedded systems is most often supplied by real-time operating systems, this approach can be unpredictable and difficult to debug. Synchronous concurrency, in which a system… (More)
- Cristian Soviani, Olivier Tardieu, Stephen A. Edwards
- IEEE Transactions on Computer-Aided Design of…
- 2006
Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pipelines, but it is… (More)
We present a new procedure for automatically synthesizing controllers from high-level Esterel specifications. Unlike existing RTL synthesis approaches, this approach frees the designer from tedious… (More)
- Cristian Soviani
- 2008
High Level Synthesis for Packet Processing Pipelines
Applying Shannon decomposition can reshape sequential circuits and improve opportunities for retiming. Both Shannon decomposition and retiming only rely on limited information about combinational… (More)
Performance-critical pipelines—such as a packet processin g pipeline in a network device—are built from a sequence of simple processing modules, connected by FIFOs. Due to their complex sequential… (More)
If a concise CFG exists for the given PDG, an optimal CFG can be efficiently generated. This is not the case for most Esterel programs. Solving the general problem optimally is NP-complete, so my… (More)
Presenting designers with higher-level specification languages is one sure way to improve productivity, but the more abstract the language, the higher the compiler’s optimization burden. We consider… (More)
State assignment is a formidable task. As designs written in a hardware description language such as Esterel inherently carry more high level information that a register transfer level model, such… (More)
- Cristian Soviani, Ilija Hadzic, Stephen A. Edwards
- 43rd ACM/IEEE Design Automation Conference
- 2006
Packet editing is a fundamental building block of data communication systems such as switches and routers. Circuits that implement this function are critical and define the features of the system. We… (More)