Craig M. Files

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In this paper, the minimization of incompletely specified multi-valued functions using functional decomposition is discussed. From the aspect of machine learning, learning samples can be implemented as minterms in multi-valued logic. The representation, can then be decomposed into smaller blocks, resulting in a reduced problem complexity. This gives induced(More)
Achieving complete delay fault testa-bility by extra inputs, " in Proc. A. Vardanian, " On completely robust path delay fault testable realization of logic functions, " in Proc. Synthesis of multi-level combinational circuits for complete robust path delay fault testability, " in Abstract—This paper presents two new functional decomposition partitioning(More)
We present an implicit approach to solve problems arising in decomposition of incompletely specified multi-valued functions and relations. We introduce a new representation based on binary-encoded multi-valued decision diagrams (BEMDDs). This representation shares desirable properties of MDDs, in particular, compactness, and is applicable to(More)
This paper considers minimization of incompletely specified multi-valued functions using functional decomposition. While functional decomposition was originally created for the minimization of logic circuits, this paper uses the decomposition process for both machine learning and logic synthesis of multi-valued functions. As it turns out, the minimization(More)
Decision trees are a widely used knowledge representation in machine learning. However, one of their main drawbacks is the inherent replication of isomorphic subtrees, as a result of which the produced classifiers might become too large to be comprehensible by the human experts that have to validate them. Alternatively, decision diagrams, a generalization(More)
Layout-driven logic synthesis combines logical and physical design to minimize interconnect length for speed-, noise-and power-critical applications. The lattice diagram synthesis approach constructs, for combinational functions, regular lattices with only local connections and input buses. Lattice diagrams are directly mappable to hardware without(More)