Corrado Villa

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Floating-gate Flash memories have been able so far to satisfy the market requirements, especially for the portable equipments, and to be the mainstream nonvolatile memory (NVM) technology [1]. Projecting into the next decade, though, there are several limitations that must be faced to further scale the floating-gate concept. The increasing complexity of(More)
NOR flash architectures continue to improve to cope with wireless application requirements of faster XIP (eXecute In Place) performance as well as faster programming throughput. A 1.8V 65nm 2b/cell 1Gb NOR flash memory [1,2] based on time-domain voltage-ramp reading concept, flexible read-while-write (RWW is presented. This paper describes the program(More)
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