Claudio Talarico

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Since the advent of new nanotechnologies, the variability of gate delay due to process variations has become a major concern.This paper proposes a new gate delay model that includes impact from both process variations and multiple input switching.The proposed model uses orthogonal polynomial based probabilistic collocation method to construct a delay(More)
A proposed modular framework for assessing power consumption of embedded systems early in the design cycle can be extended to any performance metric and uses a high level of abstraction, leading to a faster execution time. Experimental results indicate that the approach is within 20 percent of gate-level estimation and executes three orders of magnitude(More)
In heterogeneous system design, partitioning of the functional specifications into hardware (HW) and software (SW) components is an important procedure. Often, an HW platform is chosen, and the SW is mapped onto the existing partial solution, or the actual partitioning is performed in an ad hoc manner. The partitioning approach presented here is novel in(More)
A novel encryption algorithm secure to chosen-plaintext attacks is presented. As opposed to traditional key algorithms, one of the keys in the algorithm presented depends on the message itself. Two encryption matrices are generated by means of singular value decomposition (SVD), using a portion of the message. The two encryption matrices generated are(More)
This article proposes a novel methodology for robust analog/mixed-signal IC design by introducing a notion of budget of uncertainty. This method employs a new conic uncertainty model to capture process variability and describes variability-affected circuit design as a set-based robust optimization problem. For a prespecified yield requirement, the proposed(More)
In this paper we exploit the gm over ID methodology to optimize the design of a four stage conventional Distributed Amplifier (DA) for an Ultra-Wide Band positioning system. The W/L ratio and the DC-biasing of the amplifier's transistors are determined according to the gm over ID methodology by using a series of lookup tables generated starting from the(More)
This paper presents a framework for the systematic design of inductor-less regulated cascode (RGC) stages. Targeting high-speed fiber optic data receiver front-ends, the technique reported combines the symbolic solution of the small-signal model of the RGC and the use of g<sub>m</sub>/I<sub>D</sub> based lookup tables to efficiently explore and optimize the(More)
This paper presents a system level methodology for modeling, and analyzing the performance of systemon-chip (SOC) processors. The solution adopted focuses on minimizing assessment time by modeling processors behavior only in terms of the performance metrics of interest. Formally, the desired behavior is captured through a C/C++ executable model, which uses(More)
This paper introduces the design and implementation of a high performance, reconfigurable four channel beam steering unit (BSU) for active phased-array antennas based on FPGA synthesized delay-lines and PLLs. The unit allows a per channel programmable time delay equivalent to a phase shift tuning step of about 1.4&#x00B0;. A prototype has been implemented(More)