Claudio Pagnamenta

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In this paper, resonant clocking is applied to a Viterbi decoder for ultra-low-power WLAN communication. Clock skew balancing and excessive cross-over currents are identified as the most relevant issues: H-clock-trees and a new latch circuit are proposed as innovative power-efficient design solutions. The chip has been integrated in a 0.25 μm CMOS(More)
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