Claude R. Gauthier

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The development of a PowerPC™ fixed-point execution unit (FXU) in a resource limited, radiation-hard technology is described. Detailed architectural studies led to a design which maximizes performance in a small transistor count implementation. Manufactured in Motorola's 0.5—µm Complementary Gallium Arsenide process, the device operates(More)
The power delivery network is made up of passive elements in the distribution network, as well as the active transistor loads. A chip typically has three types of power supplies that require attention: core, I/O, and analog. Core circuits consist of digital circuits and have the largest current demand. In addition to all of the system issues/models for the(More)
Researchers at the University of Michigan, in collaboration with their partners from Motorola and Cascade Design Automation, are developing design methodologies and automated tools for use in implementing high clock rate digital “systems-on-anMCM.” The PUMA processor, a demonstration vehicle that executes a subset of the PowerPC instruction set, will be(More)
A self-aligned complementary GaAs (CGaAsTM) technology developed at Motorola for low-power, portable, digital and mixed-mode circuits is being extended to address highspeed VLSI circuit applications. The process supports full complementary, unipolar (pseudo-DCFL), source-coupled, and dynamic (domino) logic families. Though this technology is not yet mature,(More)
High performance I/O interface design is becoming a very important research area within VLSI. Increases in microprocessor clock frequencies have dramatically outpaced increases in I/O bandwidth, resulting in a bottleneck between processors and memory. This proposal discusses the issues relevant to high speed interface design. Studies are described that will(More)
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