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3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple(More)
This short paper explores an implementation of a new technology called 3D die stacking and describes research activity at Intel. 3D die stacking is the bonding of two die either face-to-face or face-to-back in order to construct the 3D structure. In this work, a face-to-face bonding is utilized because it yields a higher density die-to-die inter-connect(More)
Low power is considered by many as the driving force for 3D ICs, yet there have been few thorough design studies on how to reduce power in 3D ICs. In this paper, we discuss design methodologies to reduce power consumption in 3D IC designs using a commercial-grade CPU core (OpenSPARC T2 core). To demonstrate power benefits in 3D ICs, four design techniques(More)
Co-optimization between design and process is required for a highly manufacturable process technology. This paper discusses this co-optimization and how it meets the challenges for maintaining Moore's Law while delivering new processes and designs capable of fast ramp to high yields. Poly is one of the most critical layers for control of variation, and it(More)
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