Ciprian Gavrincea

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During the last century, radio dominated the world of wireless communications. One might be surprised to find out that the first voice transmission over a wireless link was done, not using radio, but using light waves. In 1880, Alexander Graham Bell demonstrated the first wireless voice communication. Bell was able to clearly communicate over a distance of(More)
The aim of this paper is to present an implementation of a functional IEEE 802.15.7 real-time testbed based on the Software Defined Radio (SDR) concept. This implementation is built with low cost commercial off-the-shelf (COTS) analog devices and the use of Universal Software Radio Peripheral version 2 (USRP2) equipment combined with a generic(More)
In this paper we propose a method to implement in FPGA circuits, a feedforward neural network with on-chip delta rule learning algorithm. The method implies the building of a neural network by generic blocks designed in Mathworks’ Simulink environment. The main characteristics of this solution are on-chip learning algorithm implementation and high(More)
In this paper, we propose a method to implement in FPGA circuit (Field Programmable Gate Array) an embedded system with on-chip learning neural network. The architecture proposed herein takes advantage of distinct modules for controlling the peripherals of the development board and for data processing as forward and backward stages of the propagation and(More)
One of the main problem in transmitting coded data is that the decoder does not know the real number of errors to correct. This issue is critical since it means that the decoders spend much more iterations for correcting them. A paradigmatic case of this is the Bose-Chaudhuri-Hocquenghem (BCH) code. This type of code generally resorts to the(More)
In this paper we propose an algorithm, implemented with VHDL language in RTL design, capable of reorganizing the f1ip-flops from within a circuit in order to reduce the power consumption through optimal c10ck distribution. Practically in the end, starting from this algoritbm, we will model the clock bebavior in a sequential circuit. Experimental results(More)
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