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In this paper we propose a method to implement in FPGA circuits, a feedforward neural network with on-chip delta rule learning algorithm. The method implies the building of a neural network by generic blocks designed in Mathworks' Simulink environment. The main characteristics of this solution are on-chip learning algorithm implementation and high(More)
One of the main problem in transmitting coded data is that the decoder does not know the real number of errors to correct. This issue is critical since it means that the decoders spend much more iterations for correcting them. A paradigmatic case of this is the Bose-Chaudhuri-Hocquenghem (BCH) code. This type of code generally resorts to the(More)
In this paper we propose an algorithm, implemented with VHDL language in RTL design, capable of reorganizing the f1ip-flops from within a circuit in order to reduce the power consumption through optimal c10ck distribution. Practically in the end, starting from this algoritbm, we will model the clock bebavior in a sequential circuit. Experimental results(More)
In this paper, we propose a method to implement in FPGA circuit (Field Programmable Gate Array) an embedded system with on-chip learning neural network. The architecture proposed herein takes advantage of distinct modules for controlling the peripherals of the development board and for data processing as forward and backward stages of the propagation and(More)
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