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Phased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360° phase shift(More)
— We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation,(More)
This session covers many aspects of contemporary Frequency Synthesizer design, both on a system and on a building block level. Improved architectures for all-digital PLLs with reduced spurious levels are introduced. This session also includes a description of improved time-to-digital converters and an improved direct digital modulation technique. Papers(More)
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