Cicero S. Vaucher

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This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the(More)
An adaptive phase-locked loop (PLL) architecture for high-performance tuning systems is described. The architecture combines contradictory requirements posed by different performance aspects. Adaptation of loop parameters occurs continuously, without switching of loop filter components, and without interaction from outside of the tuning system. The(More)
Phased arrays form a crucial step towards high data rate 60GHz wireless communication. This paper presents a fully integrated digitally controlled 60GHz RF-beamforming receiver front-end in CMOS. Using digitally controlled active phase shifters, each path of the scalable architecture achieves 10dB power gain, 7.2dB noise figure, a 360° phase shift(More)
This session covers many aspects of contemporary Frequency Synthesizer design, both on a system and on a building block level. Improved architectures for all-digital PLLs with reduced spurious levels are introduced. This session also includes a description of improved time-to-digital converters and an improved direct digital modulation technique. Papers(More)
Progress with silicon and silicon germanium based BiCMOS technologies over the past few years has been very impressive. Enabling the implementation of traditional microwave applications in silicon. As an example we present a fully integrated Ku band Phase Locked Loop (PLL) for 13.05 GHz. In this paper we analyse system choices and present measured results(More)
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