Chunyuan Zhou

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A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is(More)
The design flow of a lumped Elements varactor-loaded Transmission-Line phase shifter (VLTL) is illustrated and a 60GHz phase shifter of this kind is implemented in IBM 90nm CMOS process in this paper. The proposed VLTL is area-saving, occupying only 937um × 110um as it uses inductors instead of long transmission lines. This phase shifter is digitally(More)
A complementary injection technique is proposed to enhance the overall performance of current mode logic (CML) dividers in this paper. With injection currents introduced by pMOSFETs, the equivalent injection efficiency of CML dividers are improved and thus CML dividers achieve a better performance. Extensive simulation results show that the proposed(More)
A novel injection-locked frequency divider for V-Band frequency synthesis is proposed in this paper. Thanks to the nMOS realized in triple-well technology with N-well floating, the source and its body can be connected together to get rid of the body effect and thus reduce the nMOS threshold voltage, which helps enhance the injection efficiency in the direct(More)
A synchronous 50% duty cycle divide-by-3 divider up to 6GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the(More)
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