Chung Len Lee

Learn More
Test scheduling is an important issue for testing the SoC. This work proposes a modified shuffle frog-leaping algorithm for test scheduling to reduce the test application time under the peak power constraint. It is applied to the 2D as well as the 3D SoC and experimental results on benchmark circuits show that it is one of the most effective algorithms in(More)
An innovative long-period fiber grating (LPG) synthesis method based on the stochastic evolutionary programming (EP) algorithms is demonstrated to be effective for designing optimal LPG filters. Synthesis of a single-stage LPG filter for the entire C-band erbium-doped fiber amplifier (EDFA) gain flattening is used as an example to show the feasibility and(More)
In this paper, a Programmable Gain Amplifier (PGA) used for OOK UWB receiver is presented. It achieves a 100MHz bandwidth and a 19-40dB 8-step programmable gain. Furthermore, voltage-current DC feedback technique is adopted in order to realize DC offset cancellation (DCOC) at the output. This work is implemented in TSMC 0.18um CMOS process and consumes(More)
The advance in IC processing technology rapidly reduces spacing between adjacent wires; which renders crosstalk fault an important source of anomaly in deep subcicrom VLSI. As a result, crosstalk fault detection should be an essential part in SOC testing. Although IEEE P1500 has been developed to test interconnects in SOC. this standard is not suitable for(More)
Multilayer Data Copy (MDC) [1] is an effective test data compression scheme for achieving low shift-in power for the multiple scan chain of SoC. This work improves the scheme by employing a B-filling strategy to fill X (don't care) bits to further reduce the test data volume and the test power. Experimental results show that it can achieve more 3% of the(More)
This paper presents a sequential circuit fault simulator of “single event equivalent,” which combines advantages of techniques: the fanout-free region [ 1], the critical path tracing[2], and the dominator[3], which were only applicable to combinational fault simulation. The simulator requires minimal amount of memory, and its speed is superior to that of a(More)
  • 1