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The aggressive advent in VLSI manufacturing technology has made dramatic impacts on the dependability of devices and interconnects. In the modern manycore system, mesh based Networks-on-Chip (NoC) is widely adopted as on chip communication infrastructure. It is critical to provide an effective fault tolerance scheme on mesh based NoC. A faulty router or(More)
This paper presents a high resolution and frame rate image signal processor (ISP) array design for three-dimensional (3-D) imager. Based on the through-silicon via (TSV) technology, the short connections of the 3-D integrated circuit (IC) can improve the performance and density. Hence, the 3-D imager is the best solution for high throughput image capture or(More)
This paper presents an on-line error detection and correction techniques for through silicon via (TSV) in three-dimensional integrated circuit (3-D IC). The proposed architecture is based on biresidue codes to detect and correct the error on-line in the failed TSV over syndrome analysis. Experimental results show the proposed design has good performance in(More)
This paper presents an error-correction scheme to enhance the performance of typical CAN bus. The proposed scheme uses Reed-Solomon (R-S) codec to calculate the parity for the transmission of typical CAN bus. Compared with prior work in terms of Hybrid Automatic Repeat Request (HARQ) scheme for CAN bus transmission, the proposed scheme does not modify the(More)
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