Skip to search formSkip to main contentSkip to account menu

Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000

This work presents detailed analysis and dedicated hardware architecture of the block-coding engine to execute the EBCOT algorithm efficiently and shows that about 60% of the processing time is reduced compared with sample-based straightforward implementation.
View via Publisher (opens in a new tab)

Lifting based discrete wavelet transform architecture for JPEG2000

A lifting based 1-D discrete wavelet transform (DWT) core is proposed, a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.
View on IEEE (opens in a new tab)

Analysis and architecture design of EBCOT for JPEG-2000

Detailed analysis and efficient architecture design of Embedded Block Coding with Optimized Truncation (EBCOT) for JPEG-2000 is presented and it is shown that over 60% of processing time can be reduced by exploiting two speed-up methods.
View on IEEE (opens in a new tab)

81MS/s JPEG2000 single-chip encoder with rate-distortion optimization

An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The…
View on IEEE (opens in a new tab)

Design and implementation of JPEG encoder IP core

A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized…
View on ACM (opens in a new tab)

Hardware architecture design of an H.264/AVC video codec

By combining with many bandwidth reduction techniques and data reused schemes, very efficient architecture and implementation for plate-form based system is proved by the prototype chips.
View on ACM (opens in a new tab)

Parallel embedded block coding architecture for JPEG 2000

A parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000 is presented, based on the proposed word-level EBC algorithm, which can losslessly process 54 MSamples/s at 81 MHz and can support HDTV 720p resolution at 30 frames/s.
View on IEEE (opens in a new tab)

High speed memory efficient EBCOT architecture for JPEG2000

This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000 that can realtime encode 720p resolution of HDTV picture format at 30 fps.
View on IEEE (opens in a new tab)

On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform

A memory-efficient VLSI implementation scheme for line-based 2-D DWT, named multiple-lifting scheme, which can reduce not only at least 50% on-chip memory bandwidth but also about 50% area of line buffer in 2- D DWT module.
View on IEEE (opens in a new tab)

Effective hardware-oriented technique for the rate control of JPEG2000 encoding

By the proposed rate control method, a dedicated hardware of JPEG2000 with high-speed processing and effective rate control ability can be achieved.
View on IEEE (opens in a new tab)
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy (opens in a new tab), Terms of Service (opens in a new tab), and Dataset License (opens in a new tab)