Analysis and architecture design of block-coding engine for EBCOT in JPEG 2000
- Chung-Jr Lian, Kuanfu Chen, Hong-Hui Chen, Liang-Gee Chen
- Computer ScienceIEEE Trans. Circuits Syst. Video Technol.
- 1 March 2003
This work presents detailed analysis and dedicated hardware architecture of the block-coding engine to execute the EBCOT algorithm efficiently and shows that about 60% of the processing time is reduced compared with sample-based straightforward implementation.
Lifting based discrete wavelet transform architecture for JPEG2000
- Chung-Jr Lian, Kuanfu Chen, Hong-Hui Chen, Liang-Gee Chen
- Computer ScienceISCAS . The IEEE International Symposium on…
- 6 May 2001
A lifting based 1-D discrete wavelet transform (DWT) core is proposed, a compact and efficient DWT core for the hardware implementation of JPEG2000 encoder.
Analysis and architecture design of EBCOT for JPEG-2000
- Kuanfu Chen, Chung-Jr Lian, Hong-Hui Chen, Liang-Gee Chen
- Computer ScienceISCAS . The IEEE International Symposium on…
- 6 May 2001
Detailed analysis and efficient architecture design of Embedded Block Coding with Optimized Truncation (EBCOT) for JPEG-2000 is presented and it is shown that over 60% of processing time can be reduced by exploiting two speed-up methods.
81MS/s JPEG2000 single-chip encoder with rate-distortion optimization
- H. Fang, Chao-Tsung Huang, Liang-Gee Chen
- Computer ScienceIEEE International Solid-State Circuits…
- 13 September 2004
An 81MS/s JPEG 2000 single-chip encoder is implemented on a 5.5mm/sup 2/ die using 0.25/spl mu/m CMOS technology. This IC can encode HDTV 720p resolution at 30 frames/s in real time. The…
Design and implementation of JPEG encoder IP core
- Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang
- Computer ScienceProceedings of the ASP-DAC . Asia and South…
- 30 January 2001
A complete, low cost baseline JPEG encoder soft IP and its chip implementation are presented in this paper. It features user-defined, run-time reconfigurable quantization tables, highly modularized…
Hardware architecture design of an H.264/AVC video codec
- Tung-Chien Chen, Chung-Jr Lian, Liang-Gee Chen
- Computer ScienceAsia and South Pacific Conference on Design…
- 24 January 2006
By combining with many bandwidth reduction techniques and data reused schemes, very efficient architecture and implementation for plate-form based system is proved by the prototype chips.
Parallel embedded block coding architecture for JPEG 2000
- H. Fang, Yu-Wei Chang, T. Wang, Chung-Jr Lian, Liang-Gee Chen
- Computer ScienceIEEE transactions on circuits and systems for…
- 1 September 2005
A parallel architecture for the Embedded Block Coding (EBC) in JPEG 2000 is presented, based on the proposed word-level EBC algorithm, which can losslessly process 54 MSamples/s at 81 MHz and can support HDTV 720p resolution at 30 frames/s.
High speed memory efficient EBCOT architecture for JPEG2000
- H. Fang, T. Wang, Chung-Jr Lian, Te-Hao Chang, Liang-Gee Chen
- Computer ScienceProceedings of the International Symposium on…
- 25 May 2003
This paper presents a high speed, memory efficient architecture of embedded block coding with optimized truncation (EBCOT) tier-1 in JPEG2000 that can realtime encode 720p resolution of HDTV picture format at 30 fps.
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform
- Chih-Chi Cheng, Chao-Tsung Huang, Ching-Yeh Chen, Chung-Jr Lian, Liang-Gee Chen
- Computer ScienceIEEE transactions on circuits and systems for…
- 1 July 2007
A memory-efficient VLSI implementation scheme for line-based 2-D DWT, named multiple-lifting scheme, which can reduce not only at least 50% on-chip memory bandwidth but also about 50% area of line buffer in 2- D DWT module.
Effective hardware-oriented technique for the rate control of JPEG2000 encoding
- Te-Hao Chang, Chung-Jr Lian, Hong-Hui Chen, Jing-Ying Chang, Liang-Gee Chen
- Computer ScienceProceedings of the International Symposium on…
- 25 May 2003
By the proposed rate control method, a dedicated hardware of JPEG2000 with high-speed processing and effective rate control ability can be achieved.
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