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An Efficient Multi-Standard LDPC Decoder Design Using Hardware-Friendly Shuffled Decoding
TLDR
This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. Expand
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An Efficient Layered Decoding Architecture for Nonbinary QC-LDPC Codes
TLDR
We present an efficient layered decoder architecture for nonbinary quasi-cyclic (QC) LDPC codes using the proposed barrel-shifter-based permutation network and minimum value filter which is used to determine the first few smallest values from a given set. Expand
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A High-Throughput Trellis-Based Layered Decoding Architecture for Non-Binary LDPC Codes Using Max-Log-QSPA
TLDR
This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the QSPA sum-product algorithm in the log domain is considered. Expand
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Processing-Task Arrangement for a Low-Complexity Full-Mode WiMAX LDPC Codec
TLDR
We propose dividing the decoding operations of a variety of irregular quasi-cyclic (QC) low-density parity-check (LDPC) codes into several smaller tasks. Expand
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A Multimode Shuffled Iterative Decoder Architecture for High-Rate RS-LDPC Codes
TLDR
We propose a flexible permutator design which can be used in both multi- and single-mode decoders for RS-LDPC codes constructed based on either shortened or extended RS codes. Expand
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Selective-mapping type peak power reduction techniques for turbo coded OFDM
TLDR
In an earlier paper, a selective-mapping type turbo coded OFDM scheme was proposed, for which the interleaver of the encoder of the turbo coding can be varied to reduce the associated PAPR (peak to average power ratio) while the transmission of side information is not needed. Expand
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Jointly Designed Architecture-Aware LDPC Convolutional Codes and Memory-Based Shuffled Decoder Architecture
TLDR
We jointly design architecture-aware (AA) low-density parity-check convolutional codes (LDPC-CCs) and the associated memory-based decoder architecture based on shuffled message-passing decoding (MPD). Expand
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A shuffled message-passing decoding method for memory-based LDPC decoders
TLDR
We propose a modified shuffled message passing decoding algorithm which can achieve a similar convergence speed but with reduced complexity in memory access and storage space as compared to the conventional shuffled MPD. Expand
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VLSI decoding architecture with improved convergence speed and reduced decoding latency for irregular LDPC codes in WiMAX
TLDR
In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check code C used in the IEEE 802.16e standard. Expand
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Simultaneous temperature and pressure measurement using a packaged FBG and LPG
A new fiber sensor by using a packaged fiber Bragg grating (FBG) and long-period fiber grating (LPG) for simultaneous measurement of pressure and temperature is proposed.
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