Chung-Jay Yang

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This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the <formula formulatype="inline"> <tex Notation="TeX">$q$</tex></formula>-ary sum-product algorithm (QSPA) in the log domain is considered. We reformulate the check-node processing such that an efficient trellis-based implementation can be(More)
Compared to binary low-density parity-check (LDPC) codes, nonbinary LDPC codes have better error performance when the code length is moderate. This paper presents an efficient layered decoder architecture for nonbinary quasi-cyclic (QC) LDPC codes using the proposed barrel-shifter-based permutation network and minimum value filter which is used to determine(More)
This paper presents an efficient multi-standard low-density parity-check (LDPC) decoder architecture using a shuffled decoding algorithm, where variable nodes are divided into several groups. In order to provide sufficient memory bandwidth without the need for using registers, a FIFO-based check-mode memory, which dominates the decoder area, is used. Since(More)
For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed-Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check(More)
In this paper, we jointly design architecture-aware (AA) low-density parity-check convolutional codes (LDPC-CCs) and the associated memory-based decoder architecture based on shuffled message-passing decoding (MPD). We propose a method for constructing AA-LDPC-CCs that can facilitate the design of a memory-based shuffled decoder using parallelization in(More)
The convergence speed of shuffled message passing decoding (MPD) is faster than that of standard two phase message passing (TPMP) decoding. Due to complex memory access and requirement of large storage space, the shuffled MPD is not suitable for hardware implementation especially for high-rate LDPC codes. In this paper, we propose a modified shuffled MPD(More)
In an earlier paper, a selective-mapping type turbo coded OFDM scheme was proposed, for which the interleaver of the encoder of the turbo coding can be varied to reduce the associated PAPR (peak to average power ratio) while the transmission of side information is not needed. In this paper, we propose two modified versions of that scheme. For the first, the(More)
In this paper, we propose dividing the decoding operations of a variety of irregular quasi-cyclic (QC) low-density parity-check (LDPC) codes into several smaller tasks. An algorithm is devised in order to arrange these tasks in a similar form such that a highly reusable multimode architecture can be designed to process these tasks. For this task-based(More)
In this paper, we modify a previously proposed decoding algorithm and propose a VLSI architecture to decode the quasi-cyclic low-density parity-check (QC-LDPC) code C used in the IEEE 802.16e standard. The modified decoding algorithm sequentially decodes a plurality of block codes for which its code length is much smaller than that of C. The proposed(More)
In this paper, we present a low-complexity decoder architecture for WiMAX low-density parity-check (LDPC) codes based on a unified task processor. Memory access is accomplished through routing networks with fixed interconnections and memory address generators, which are quite simple due to the quasi-cyclic structure of the LDPC codes. In order to increase(More)