Chung-Han Chou

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Preconditioned Conjugate Gradient (PCG) method has been demonstrated to be effective in solving large-scale linear systems for sparse and symmetric positive definite matrices. One critical problem in PCG is to design a good preconditioner, which can significantly reduce the runtime while keeping memory usage efficient. Universal preconditioners are simple(More)
As the supply voltage is down to the ultra-low voltage (ULV) level, timing closure becomes a serious challenge in the use of multiple power modes. Due to a wide voltage range, a very huge clock skew may occur among different power modes. To reduce this huge clock skew, the conventional power-mode-aware clock tree often suffers from a huge overhead on power(More)
To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among(More)
Thermal integrity is one of the most important challenges faced by three-dimensional integrated circuits (3D ICs). Towards this, thermal through-silicon-vias (TTSVs) have been widely used to assist heat dissipation. The metal inside TTSVs can conduct heat more effectively than the silicon substrate, and the metal bumps underneath TTSVs can help heat(More)
To conserve energy, a design which utilizes different power modes has been widely adopted. However, when a design has many different power modes, clock tree optimization (CTO) becomes very difficult. In this paper, we propose a two-level power-mode-aware CTO methodology. Among all different power modes, the chip-level CTO globally reduces clock skew among(More)
In advanced technologies, on-chip-variation (OCV) has accounted for a large proportion of clock skew, which limits the performance of a circuit. To mitigate the OCV problem, a mesh structure has been widely used in high-performance designs. Unfortunately, clock mesh structure also causes large power consumption and large power-ground surge current.(More)
In a multipower-mode design, as the range of the supply voltage becomes wide, a large clock skew may occur among different power domains. To remove this clock skew, conventional power-mode-aware buffers (PMABs) require a large overhead on power consumption. In this brief, we propose a new PMAB architecture for wide-voltage-range multipower-mode designs. The(More)
Glioblastomas are among the most fatal brain tumors; however, the molecular determinants of their tumorigenic behavior are not adequately defined. In this study, we analyzed the role of KMT2A in the glioblastoma cell line U-87 MG. KMT2A knockdown promoted cell proliferation. Moreover, it increased the DNA methylation of NOTCH1 and NOTCH3 and reduced the(More)
This paper introduces CN-SIM, a cycle accurate, full system, power delivery (PD) noise simulator. CN-SIM provides a cross layer connectivity form application layer, to the architecture layer, to the circuit layer, which is much needed to realistically estimate PD noise. Thus, making it easier for system architects to explore multilayer design optimizations.(More)
Preconditioned Conjugate Gradient (PCG) method has been demonstrated to be effective in solving large-scale linear systems for sparse and symmetric positive definite matrices. One critical problem in PCG is to design a good preconditioner, which can significantly reduce the runtime while keeping memory usage efficient. Universal preconditioners are simple(More)