Chune-Sin Yeh

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The age reliability of the RF performance of CMOS radio chips must be validated prior to high volume manufacturing. In this paper, we show the results of age simulations on some RF subblock designs used in our 802.11 a/b/g radio chip transceiver for our WLAN card. Transistor age models, based on HCI and NBTI age degradation mechanisms, were derived from(More)
This paper presents a new aged timing simulation methodology that can be used for hot-carrier reliability assurance of VLSI. This methodology consists of a compact model and a unique algorithm. The ratio based model simplifies the aging I-V characteristics of MOSFET over time into the aged timing and the corresponding ratio at gate-level. A new algorithm is(More)
A simulation system is described for linking two-dimensional simulators for process and device to a parameter extraction program, for the purpose of generating artificial parameters for the circuit analysis program, NASPICE. A key feature of the system is that it operates under the control of a shell program which offers a simple and easy to use interface(More)
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