Chun-Yeh Liu

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A new method for designing a Built-In Self-Test Programmable Logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a re-arrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA. The BIST-PLA(More)
Programmable Logic Arrays (PLA's) provide a flexible and efficient way of synthesizing arbitrary combina-tional functions as well as sequential logic circuits. They are used in both LSI and VLSI technologies. The disadvantage of using PLA's is that most PLA's are very sparse. The high sparsity of the PLA results in a significant waste of silicon area. PLA(More)
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