Learn More
—This paper presents an architecture for a recon-figurable device that is specifically optimized for floating-point applications. Fine-grained units are used for implementing control logic and bit-oriented operations, while parameterized and reconfigurable word-based coarse-grained units incorporating word-oriented lookup tables and floating-point(More)
This paper describes a novel hardware accelerator for Monte Carlo (MC) simulation, and illustrate its implementation in field programmable gate array (FPGA) technology for speeding up financial applications. Our accelerator is based on a generic architecture , which combines speed and flexibility by integrating a pipelined MC core with an on-chip(More)
Embedded elements, such as block multipliers, are increasingly used in advanced field programmable gate array (FPGA) devices to improve efficiency in speed, area and power consumption. A methodology is described for assessing the impact of such embedded elements on efficiency. The methodology involves creating dummy elements, called virtual embedded blocks(More)
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and(More)
We present an architecture for a synthesizable datapath-oriented Field Programmable Gate Array (FPGA) core which can be used to provide post-fabrication flexibility to a System-on-Chip (SoC). Our architecture is optimized for bus-based operations that are common in signal processing and computation intensive applications. It employs a directional routing(More)
Computer arithmetic is a specialist field of study, and it is very difficult for designers to choose the most efficient method for implementing a given algorithm due to the large number of design choices available. In this paper, an object oriented arithmetic library is presented which can be used to simulate and generate designs which use fixed, floating,(More)
In this paper we present the " fly " hardware compiler for rapid system prototyping research. Fly takes a C-like program as input and produces a synthesizable VHDL description of a one-hot state machine and the associated data path elements as output. Furthermore, it is tightly integrated with the hardware design environment and implementation platform, and(More)
A system for the rapid prototyping of floating point hardware designs is presented. This system, called Float, consists of a floating point class for the simulation of quanti-zation effects associated with low precision floating point operators; an optimizer which can automatically determine the minimal number of exponent and fraction bits required for a(More)
A hybrid FPGA consists of island-style fine-grained units and domain-specific coarse-grained units. This paper describes an approach to estimate the power consumption of a set of hybrid FPGA architectures. The dynamic power consumption of the fine-grained units is obtained using standard FPGA tools, and the coarse-grained units using standard ASIC tools.(More)