Learn More
This work presents an interpolated flying-adder-(FA-) based frequency synthesizer. The architecture of an interpolated FA, which uses an interpolated multiplexer (MUX) to replace the multiplexer in conventional flying adder, improves the cycle-to-cycle jitter and root-mean-square (RMS) jitter performance. A multiphase all-digital phase-locked loop (ADPLL)(More)
A new source follower circuit using low-temperature polycrystalline silicon thin film transistors (LTPS-TFTs) as analog buffer for the integrated data driver circuit of active matrix liquid crystal displays (AMLCDs) and active matrix light emitting diodes (AMOLEDs) is proposed and measured. Threshold voltage compensation circuit with two n-type thin film(More)
The effects of active layer thickness and device dimensions on nanometal-induced crystallization (nano-MIC) were studied to determine the electrical characteristics of the polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with bottom-gate structures. The nano-MIC poly-Si film was obtained via deposition of a 0.4-nm-thick Ni film on the(More)
High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls(More)
Pulsed-laser deposited (Pb,Sr)TiO(3) (PSrT) films on Pt/SiO(2)/Si substrate at various ambient oxygen pressures (P(O(2))) are investigated in this work. Films deposited at P(O(2)) below 100 mTorr exhibit the (100) preferred orientation and a tetragonal structure with larger tetragonality. In addition, films deposited at 80 mTorr exhibit the most apparent(More)
Electrostatic discharge (ESD) protection and latchup prevention are two important reliability issues to the CMOS integrated circuits, especially in high-voltage (HV) applications. In this work, the stacked low-voltage (LV) PMOS devices have been successfully verified in a 0.5-μm HV process to provide high ESD level with high holding voltage for HV(More)
  • 1